1. Field of the Invention
The present invention relates generally to a fabrication process of a semiconductor device with a wiring structure. More specifically, the invention relates to an improvement of a structure of a contact hole for electrode wiring and formation process therefor.
2. Description of the Related Art
Down-sizing and higher density packaging of semiconductor elements is still actively on-going. Nowadays, an ultra-high package density semiconductor device, such as 256 Mbits DRAM (dynamic random access memory) designed under 0.25 .mu.m of dimensional standard has been developed and experimentally fabricated. Associated with increasing packing density of the semiconductor devices, a strong demand is growing for reduction or elimination of margin for mask alignment in lithography process which is essential process in fabrication of semiconductor element structures.
Normally, in fabrication of the semiconductor devices, semiconductor elements of fine structures are formed by sequentially stacking patterns of various materials, such as metal film, semiconductor film, insulation layer and so forth. Upon stacking patterns for semiconductor elements, in lithography process, it is required to align a mask to a lower layer pattern formed in the preceding process and to subsequently form a upper layer pattern. However, in the lithography process, it is possible to cause position error between the upper layer and the lower layer. Therefore, it becomes necessary to provide a margin of tolerance in an interval of the pattern on the mask by taking such position error into account. However, such a margin inherently borders increasing of package density.
Therefore, study has been started for marginless technology to make such a margin in the interval of the pattern unnecessary. It is particularly important to make formation of a contact hole marginless. The contact hole is frequently formed through various layers on a semiconductor substrate, a semiconductor layer and a metal layer. To make formation of the contact hole marginless represents the most effective technique for increasing of package density of the semiconductor device. One dominant method for marginless technology is a self-aligned type contact hole formation process. Various concrete methods in this regard have been studied. For example, Japanese Unexamined Patent Publication (Kokai) No. Heisei 3-21030 shows one example of such methods.
FIGS. 1A to 1D are cross sections showing a sequence of process steps for forming a self-aligned type contact hole on the semiconductor substrate disclosed in the above-identified Japanese Unexamined Patent Publication No. Heisei 3-21030.
As shown in FIG. 1A, a plurality of insulated-gate type field effect transistors are provided on the surface of a silicon semiconductor substrate 41. In these insulated-gate type field effect transistors, circumferences of the adjacent gate electrodes 42 and 42a are coated with coating oxide layer 43 and 43a. Also, the overall surface of the semiconductor substrate 41, on which are formed a diffusion layer 44 to be the sources and drains of the insulated-gate type field effect transistors and an isolation oxide layer 45, is coated by an etch buffer insulation layer 46. Here, the coating oxide layer 43 and 43a and the etch buffer insulation layer 46 are formed with silicon oxide layers and silicon nitride layer, respectively.
Next, after forming insulation layer 47 with a silicon oxide layer including a boron glass or phosphorous glass (hereinafter referred to as "BPSG layer"), selective etching of the interlayer insulation layer 47 is performed with a photoresist 48 as a mask. This etch is a wet etching with a fluoric acid type chemical liquid. The etching buffer insulation layer 46 is formed with the silicon nitride layer having etching resistance against fluoric acid. Therefore, etching of this insulation layer is not substantial in extent. Then, only interlayer insulation layer 47 is etched to form a diffusion layer contact hole 49 being formed.
Next, as shown in FIG. 1C, the portion of the etch buffer insulation layer 46 not covered by the insulation layer 47 is selectively etched for removal. In this case, in order to avoid progress of etching in the coating oxide layer 43 and 43a, the etching has to be performed under a dry etching condition. Thus, the diffusion layer contact hole 49a exposing the diffusion layer 44 on the surface is formed.
Finally, as shown in FIG. 1D, a wiring layer 50 is formed. As shown in FIG. 1D, the diffusion layer contact hole 49a on the semiconductor substrate is formed in a self-aligned manner in the gate electrodes 42 and 42a coated with coating oxide layers 43 and 43a. Thus, via the diffusion layer contact hole 49a, the wiring layer 50 is electrically connected to the diffusion layer 44 and is insulated from the gate electrodes 42 and 42a via the coating insulation layer 43 and 43a.
The above-mentioned wiring structure formation method is the formation method for a self-aligned type contact hole for connection of the impurity diffusion layer 44 formed on the silicon semiconductor substrate 41 and the upper wiring layer 50. However, in the normal semiconductor device, the gate electrode is formed as wiring. Thus, it is essential that the wiring of the gate electrode and the upper layer wiring are electrically connected. In order to satisfy such requirement with the above-mentioned prior art, it becomes necessary to have a contact hole formation process performed separately from the self-aligned type contact hole formation process. Therefore, it is desired in view point of shortening of the process to form the contact hole on the wiring of the gate electrode simultaneously with formation of the self-aligned type contact hole.
Furthermore, when the silicon nitride layer is employed as the etching buffer insulation layer 46 as in the prior art shown in FIGS. 1A to 1D, electrification of charge in the insulation layer below the wiring 50 can be caused. This is because that charge may be accumulated at the interface between the coating oxide layers 43, 43a and the etching buffer layer 46, the interface between the interlayer insulation layer and the etching buffer insulation layer and so forth. The electrifying of charge in the insulation layer will degrade reliability of the semiconductor device. Such electrifying is caused by virtue of the same principle as attributable to accumulation of charge in the interface of the oxide layer and nitride layer in the MNOS (metal-nitride layer-oxide layer-semiconductor) as non-volatile memory device.
Also, since the silicon nitride layer is not permeable to hydrogen, difficulty is encountered in hydrogen alloying of the semiconductor device. Hydrogen alloying is performed after completion of metallization as final process in fabrication of the semiconductor device to make the interface between the silicon oxide layer and the silicon semiconductor substrate electrically inactive for stabilization. If this process cannot be performed, a threshold voltage of a insulated-gate type field effect transistor is unstable. Also, junction leak current at the interface region of the diffusion layer 44 and the isolation oxide layer 45 can be increased. Increase of the leak current is critical for increasing packing density of the semiconductor device. Therefore, solution of this problem is imperative.
In addition, the silicon nitride layer may cause large thermal stress to the silicon semiconductor substrate. Consequently, in the thermal process in the semiconductor device fabrication process, a crystal defect may be caused in the silicon semiconductor substrate. Such an inductive defect is caused at a certain rate to lower the yield in the semiconductor device fabrication process.